base+4 ... base+2 base number of bits
..xxxx xxxxxxxxxxxxxxxx xnnnxxxxx1111111 (80+16*nnn)-bit, nnn!=111
{ops}{Pred}{Reg}{VL Block} VBLOCK Prefix

A suitable prefix, which fits the Expanded Instruction-Length encoding for "(80 + 16 times instruction-length)", as defined in Section 1.5 of the RISC-V ISA, is as follows:

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vlset 16xil rplen pplen pmode rmode 1111111

The VL/MAXVL/SubVL Block format, when 16xil != 0b111, is:

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0b00 SubVL imm[5:0] rsvd 00000 VL = MIN(MVL, imm)
0b00 SubVL imm[5:0] rsvd rd[4:0] rf[rd] = VL = MIN(MVL, imm)
0b01 SubVL imm[5:0] rs1[2:0] rd[2:0] RVC reg format, sv.setvl rd, rs, imm
0b10 SubVL imm[5:0] rsvd 00000 VL = MVL imm
0b10 SubVL imm[5:0] rsvd rd[4:0] rf[rd] = VL = MVL imm
0b11 rsvd rsvd rsvd rsvd reserved, all 0s

When 16xil is 0b111, this is the "Extended" Format, using the >= 192-bit RISC-V ISA format. Note that the length is 96+16*nnnnnn, not 192+

base+5 ... base+3 base+1 base no. of bits
..xxxx xxxxxxxxxxxxxxxx x111xxxxx1111111 96+16*nnnnnn
{ops}{Pred}{Reg}{VL Block} VBLOCK2 VBLOCK Prefix

VBLOCK2 extends the VBLOCK fields:

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rsvd rplen2 pplen2 swlen ilen
  • ilen is the instruction length (number of 16-bit blocks)
  • swlen specifies the number of "swizzle" blocks
  • rplen2 extends rplen by 2 bits
  • pplen2 extends pplen by 2 bits