Welcome to Libre-SoC!

Libre-RISCV is an effort to develop an completely open/Libre SOC that is open to the bedrock!

This is a publicly editable wiki.

All wikis are supposed to have a SandBox, so this one does too.

This wiki is powered by ikiwiki.

This is the sitemap: sitemap

Joining/Onboarding Process

This process probably needs some improvement, but the basic idea is to join the mailing list, introduce yourself, and read through recent posts and the charter.

The next thing you should do is read through the bugs list and see if there are any bugs that pique your interest.

We do have funding available (see nlnet) upon completion of issues - we are also working on procuring more funding which gets the project to nanometre scale tapeout.

Needed Skills

Most labor is currently being applied to developing the GPU portion of the LibreSOC.

The highest priority needed at the moment is a c++ engineer to work on a MESA 3D driver. This will begin life as similar to SwiftShader however retaining the vectorisation and predication intrinsics.

Medium to long-term we need HDL engineers. Particularly those familiar with nMigen or just python. Most of the techniques being used require software engineering skills (OO design, polymorphism) than they do more traditional HDL programming skills. Basically if you have experience in 2 of the following you'll do fine: python, nmigen, verilog/VHDL/gate-level design. See HDL workflow

Also, individuals with experience in formal mathematical verification are quite welcome.

TODO: add a list of upcoming project tasks/milestones (link to bugtracker).


Main Pages

Spike Emulator

Current Members

current members