ISA Pseudo-code

ISA is the Instruction set architecture of a machine, the: CPU instructions, register set, memory model, etc, that describe the way a machine works.

These pages contain (in a strict machine-readable subset of mdwn) the pseudo-code for all opcodes in the POWER v3.0B Public Spec

• bcd
• branch
• comparefixed
• condition
• fixedarith
• fixedload
• fixedlogical
• fixedshift
• fixedstore
• fixedtrap
• sprset
• stringldst
• system

FP instructions: useful for testing http://weitz.de/ieee/

• fpload
• fpstore
• fpmove
• fparith
• fpcvt

Scalar instructions added as part of svp64 development, these are all DRAFT FORM and they are all stand-alone Scalar (no hard dependency on Simple-V). Explanation of the rules for twin register targets (implicit RS, FRS) explained in SVP64 appendix

• svfixedarith
• svfparith
• bitmanip
• av - Audio/Video includes minmax, sum of absolute difference etc.

Scalar "Post-Increment" Draft Load/Store with Update

• pifixedload
• pifixedstore
• pifpload
• pifpstore

Scalar "Post-Increment" Draft Load/Store with Shift

• pifixedloadshift
• pifixedstoreshift
• pifploadshift
• pifpstoreshift

Part of the DRAFT Simple-V Specification:

• simplev

A useful aide to finding Power ISA instructions: https://power-isa-beta.mybluemix.net

Pseudocode syntax

The syntax is shown in the v3.0B OpenPOWER Reference Manual. The implementation of a parser, using python-ply, is here: https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/pseudo/parser.py;hb=HEAD

The parser is based on the python-ply GardenSnake.py example (except bugs were fixed in it, first). Extra tokens, in the lexer phase, are inserted dynamically into the stream to make the parser think that it is seeing python-like syntax where in fact it is not. Example: when a pseudocode keyword "THEN" is seen, this is substituted for ":". The keyword "ELSE" will also automatically have a second ":" token inserted in order to comply with python syntax. Thus the following pseudocode:

if x = 1 then
   RT <- 1
else
   RT <- 0

results in the parser seeing the following python code:

if x == 1:
   RT = 1
else
   RT = 0

To support this python-like syntax some of the pseudocode after extraction from the PDF had to be cleaned up and proper indentation added.

Also worth noting as used in the above example: the following operators are used (see section 1.3 "Notation" of v3.0B PDF):

• <- assignment, instead of "=" as in python
• = equals comparator, instead of "==" as in python
• || concatenate, done bitwise, in MSB0 order.
• >u for unsigned greater (">" is signed)
• <u for unsigned lessthan ("<" is signed)
• X superscript n subscript is instead expressed [X]*n
• X subscript n or n:m is expressed as X[n:m]

The reason for the addition of the unsigned comparator operators is because numbers in the pseudocode are bitpatterns, not assigned a type or a sign as would normally be done in a standard programming language