180nm Test ASIC

This is a single-core, non-SMP, no analog PLLs, no clock-gating, test ASIC, expected to run at one-to-one from an external 24 mhz to 100 mhz clock.

The requirements are therefore radically different from the next roadmap ASIC.

Basic diagram:

Eight LD/ST Function Units with 2 ports each (one for aligned, one for misaligned), each connecting to one of a pair of L0 Cache/Buffers. Addr[4] determines which L0 Cache/Buffer to connect to.
A L0 Cache/Buffer with dual 8x 128-bit-wide entries and a single-clock, single-path outgoing read or write protocol, with 8 pairs of (individual, non-multiplexed) incoming 128-bit entries where each pair is hard-required to have the same top bits (12-48). The left port has address bit 4 set to zero, the right port to 1.
The L0 Cache/Buffer connects to a pair of 128-bit data paths to a standard non-SMP-aware L1 cache. The data in and out on each port is again read or write, 128-bit-wide.
A pair of Wishbone "funnels" take the 128-bit requests, which include byte-level access lines, and if needed create a pair of 64-bit Wishbone-compliant requests. "If needed", because if the lower half (or upper half) byte-level access lines are not set, then that indicates a 64-bit request, and thus only one request is needed. Only when byte-access lines in both upper and lower halves are set will two requests be needed
Standard Wishbone 64-bit Bus. This is where Enjoy-Digital Litex code takes over, and connect to peripherals and testing infrastructure.
Memory is the silicon-proven OpenCores ?SDRAM interface, and it is Wishbone compliant.

Memory Interface Required by LDSTComputationalUnit

See https://bugs.libre-soc.org/show_bug.cgi?id=216#c26. Other signals (type of LD/ST: atomic or I/O, type of exception) left out for brevity

Common to LD/ST:

LD:

ST:

Source: PortInterface

This is full SMP, requires analog PLLs, clock gating, full SMP L1 and L2 cache coherency and atomic coherency.

TODO

TODO