Tuesday 28th November 17:00 UTC

Main Agenda

reminder to everyone to fill in their links to bugreports now (right now) on the previous meeting if not already done so. you are responsible for maintaining your own "section" notes in each minutes. format: [bug #NNNN](https://bugs.libre-soc.org/show_bug.cgi?id=NNNN)
reminder of Dec 1st deadline for FOSDEM 2024 talk proposal submissions. abstract can be very short, edit later. do not leave it to last minute! new system in place. bug #1070 https://lists.libre-soc.org/pipermail/libre-soc-dev/2023-November/005798.html
reminder of only three months (13 weeks) until march 1st deadline for completion of cavatools and cryptoprimitives. all tasks scope must be cut right back, do not spend hours "attempting to struggle" out of a futile "i must achieve it alone" ethos: ASK FOR HELP IMMEDIATELY
Clarification of the scope of new grants. See dmitry 2023-11-24 notes for more context.

Meeting notes:

Deprecated SimpleV prefix format from 2019: https://libre-soc.org/simple_v_extension/sv_prefix_proposal/
RISC-V example extension: https://github.com/riscv-software-src/riscv-isa-sim/blob/master/customext/cflush.cc
The first step is to make modifications to sv_analysis.py to classify the RISC-V instructions. https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/sv/sv_analysis.py;hb=HEAD
Standard RISC-V opcode format: https://github.com/riscv/riscv-opcodes
bug #980
- A lot of work, need to focus on the basics
- Issues with current Python pseudo-code compiler:
  - pseudocode is full of python-isms such as some variables are python ints and some are selectableint and some are strings etc.
  - plus, the parser currently has wrong operator precedence bug #1082.
- Suggested minimal goal for bug #980 is:
  - Use AST (operands, flow, etc. as we already do for generated Python func's) and a custom visitor function to convert to C code.
  - Generate C functions which can be compiled without errors.
  - Generated functions can be run from a main function to confirm results.
  - Jacob suggested using maddedu as a benchmark, since it has non-trivial pseudo-code.

Update bug #1126 to include git commit descriptions.
Check whether RISC-V have their own way of describing the instructions (likely they do).
Familiarise yourself with svanalysis.py, as we will need a similar tool for RISC-V.
Check what RISC-V support in binutils looks like. Needed for confirming the details of the RISC-V binutils grant.

Check with Dmitry on git commit descriptions (bug #1126). Once comment made, add to HDL workflow documentation.

bug #672 long story, pospopcount needs bmatflip (aka vgbbd in VSX) but also needed sv.bc fixing bug #1215 which is related/similar to the DDFFirst issue on scalar source/dest bug #1183 which jacob also noted for sv.cmpi/ff needed on bigmul.
Guide Dmitry on svanalysis.py.
Guide Shriya in Poly1305 bug #1157 and ED25519 bug #1151 to assist Sadoon.