Resources and Specifications

This page aims to collect all the resources and specifications we need in one place for quick access. We will try our best to keep links here up-to-date. Feel free to add more links here.

RISC-V Instruction Set Architecture

The Libre RISC-V Project is building a hybrid CPU/GPU SoC. As the name of the project implies, we will be following the RISC-V ISA due to it being open-source and also because of the huge software and hardware ecosystem building around it. There are other open-source ISAs but none of them have the same momentum and energy behind it as RISC-V.

To fully take advantage of the RISC-V ecosystem, it is important to be compliant with the RISC-V standards. Doing so will allow us to to reuse most software as-is and avoid major forks.

Note: As far as I know, we aren't using the RISC-V V Extension directly at the moment. However, there are many wiki pages that make a reference to the V extension so it would be good to include it here as a reference for comparative/informative purposes with regard to Simple-V.

IEEE Standard for Floating-Point Arithmetic (IEEE 754)

Almost all modern computers follow the IEEE Floating-Point Standard. Of course, we will follow it as well for interoperability.

Note: Even though this is such an important standard used by everyone, it is unfortunately not freely available and requires a payment to access. However, each of the Libre RISC-V members already have access to the document.

Khronos Standards

The Khronos Group creates open standards for authoring and acceleration of graphics, media, and computation. It is a requirement for our hybrid CPU/GPU to be compliant with these standards as well as with IEEE754, in order to be commercially-competitive in both areas: especially Vulkan and OpenCL being the most important. SPIR-V is also important for the Kazan driver.

Thus the zfpacc proposal has been created which permits runtime dynamic switching between different accuracy levels, in userspace applications.

SPIR-V Main Page https://www.khronos.org/registry/spir-v/

Vulkan Main Page https://www.khronos.org/registry/vulkan/

OpenCL Main Page https://www.khronos.org/registry/OpenCL/

Note: We are implementing hardware accelerated Vulkan and OpenCL while relying on other software projects to translate APIs to Vulkan. E.g. Zink allows for OpenGL-to-Vulkan in software.

Graphics and Compute API Stack

I found this informative post that mentions Kazan and a whole bunch of other stuff. It looks like many APIs can be emulated on top of Vulkan, although performance is not evaluated.

https://synappsis.wordpress.com/2017/06/03/opengl-over-vulkan-dev/

Free Silicon Conference

The conference brought together experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference covered the full spectrum of the design process, from system architecture, to layout and verification.

Note: The rest of LIP6's website is in French, but there is a UK flag in the corner that gives the English version.

The OpenROAD Project

OpenROAD seeks to develop and foster an autonomous, 24-hour, open-source layout generation flow (RTL-to-GDS).

Other RISC-V GPU attempts

TODO: Get in touch and discuss collaboration

Tests, Benchmarks, Conformance, Compliance, Verification, etc.

RISC-V Tests

RISC-V Foundation is in the process of creating an official conformance test. It's still in development as far as I can tell.

  • //TODO LINK TO RISC-V CONFORMANCE TEST

IEEE 754 Tests

IEEE 754 has no official tests for floating-point but there are several well-known third party tools to check such as John Hauser's SoftFloat and TestFloat.

Jacob is also making a Rust library to check IEEE 754 operations.

A cool paper I came across in my research is "IeeeCC754++ : An Advanced Set of Tools to Check IEEE 754-2008 Conformity" by Dr. Matthias Hüsken.

Khronos Tests

OpenCL Conformance Tests

Vulkan Conformance Tests

MAJOR NOTE: We are not allowed to say we are compliant with any of the Khronos standards until we actually make an official submission, do the paperwork, and pay the relevant fees.

Formal Verification

Formal verification of Libre RISC-V ensures that it is bug-free in regards to what we specify. Of course, it is important to do the formal verification as a final step in the development process before we produce thousands or millions of silicon.

Some learning resources I found in the community:

ZipCPU provides a comprehensive tutorial for beginners and many exercises/quizzes/slides: http://zipcpu.com/tutorial/

https://tomverbeure.github.io/risc-v/2018/11/19/A-Bug-Free-RISC-V-Core-without-Simulation.html

https://tomverbeure.github.io/rtl/2019/01/04/Under-the-Hood-of-Formal-Verification.html

Libre-RISC-V Standards

This list auto-generated from a page tag "standards":

ld.x
Posted Thu Oct 3 14:36:00 2019
vector ops
Posted Mon Sep 16 09:13:30 2019
bitmanip
Posted Sat Sep 7 13:30:19 2019
zfpacc proposal
Posted Fri Aug 9 05:38:34 2019
ztrans proposal
Posted Mon Aug 5 06:17:19 2019
sv.setvl
Posted Wed Jun 26 09:12:44 2019
mv.x
Posted Wed Jun 26 08:04:09 2019
remap
Posted Tue Jun 25 14:21:45 2019
appendix
Posted Tue Jun 25 12:43:53 2019
abridged spec
Posted Tue Jun 25 11:16:43 2019
vblock format
Posted Tue Jun 25 11:16:43 2019
sv prefix proposal
Posted Mon Jun 17 07:29:06 2019
specification
Posted Tue Mar 26 02:43:14 2019